LH5332500 Search Results

a5c capacitor

Abstract: TM 1218 48-PIN A17C LH5332500BN TSOP048-P-1218 12X18 SAA 1220
Contextual Info: LH5332500B FEATURES CMOS 32M 4M x 8/2M x 16 M ask-Program m able ROM PIN CONNECTIONS • 4,194,304 words x 8 bit organization (Byte mode) 2,097,152 words x 16 bit organization (Word mode) 44-PIN SOP 1• 44 ~3 a 20 2 43 ^ A 17 C 3 42 Zl Ag • Static operation

Contextual Info: PRELIMINARY LH5332500 FEATURES • 4,194,304 x 8 bit organization Byte mode 2,097,152 x 16 bit organization (Word mode) • BYTE input pin selects bit configuration • Access time: 150 ns (MAX.) CM O S 32M (4M x 8 / 2M x 16) M a s k -P ro g ra m m a b le ROM

LH5332500B

Contextual Info: LH5332500B FEATURES CMOS 32M 4M x 8/2M x 16 Mask-Programmable ROM PIN CONNECTIONS • 4,194,304 words x 8 bit organization 2,097,152 words x 16 bit organization (Word mode) • Access time: 150 ns (MAX.) • Power consumption: Operating: 357.5 mW (MAX.)

44-PIN

Abstract: 48-PIN
Contextual Info: CMOS 32M 4M x 8/2M × 16 Mask-Programmable ROM LH5332500B FEATURES • 4,194,304 words × 8 bit organization (Byte mode) 2,097,152 words × 16 bit organization (Word mode) • Access time: 150 ns (MAX.) • Power consumption: Operating: 357.5 mW (MAX.)

sharp mask rom 44-pin

Contextual Info: PRELIMINARY LH5332500 CMOS 32M 4M x 8/2 M x 16 Mask-Programmable ROM FEATURES DESCRIPTION • 4,194,304 x 8 bit organization The LH5332500 is a mask-programmable ROM organized as 4,194,304 x 8 bits (Byte mode) or 2,097,152 x 16 bits (Word mode) that can be selected

LHMN5

Abstract: 48TSOP LH5332600 LH5332600N LH5332600T LH5332C00D TSOP048-P-1218 LH5332500 2sj au LHMV
Contextual Info: NBA/ INFORMATION LH5332600 • High-speed 32M-bit Mask-Programmable ROM Pin Connections Description The LH5332600N/T User's No. : LHMN56XX/LHMN5FXX is a CM OS 32M-bit mask-programmable ROM organized as 4 194 304X8 bits (Byte mode) or 2 097 152X 16 bits (Word

536G

Abstract: LH534600
Contextual Info: MEMORIES • Mask ROMs Process Capacity * Configuration words X bits Pinout Access time Model No. (ns) MIN. Supply current (mA) MAX. Supply voltage (V) (ns) MAX. User's No. Cycle tima Package 256k 32k X 8 J LH53259D/N/T L H 5359X X 150 25 5 ± 10% 28DIP/28SOP/28TSOP(I)

lh57257

Abstract: IR2E31 IR2E01 IR2C07 IR2E27 IR2E24 IR2E19 IR2E31A IR3n06 IR2E02
Contextual Info: Index Model No. ARM7D CPU Core Bi-CMOS 1 27 40,42 _ _ CMOS CMOS CMOS CMOS CMOS 4A 5A 8 A AH D ID1 Series ID2 Series 40,42 40.42 40,42 40,42 40 B ü.’1*"! 14,15 14 m IR2339 IR2403 IR2406 IR2406G IR2410 IR2411 IR2415 IR2419 IR2420 IR2422 IR2425 IR2429

LH231G

Abstract: lh5348 LH538b LH2326 lh5s4 LHMN5 lh5359 lh5348xx lh537 LH235
Contextual Info: MEMORIES ★Under development • M ask ROMs SlpÉHRfi Bonflgmllan jvorai x d m i NMOS <"^g|g|ï|ïi£- User1* No. sssysr Sllpjiijp 1 currant mA MAX. ■ Paefcagfe ft- • 64k 8k x 8 LH2389D LH2369XX 200 60 5 ± 10% 28DIP 128k 16k x 8 LH23128D LH2326XX 200

lh537

Abstract: 42DIP lh533200 LH535g
Contextual Info: MEMORIES • Mask ROMs Process CMOS ★ U n d e r development MEMORIES ★ Under developm ent Configuration Process Capacity (wortsxbits Access time (ns) MAX. Model No. Pinout LH-538VXX 100 100 5 ± 10% 32DIP/32SOP/32TSOPÎII) Normal 120 60 5 ± 10% L H 5 3 8 3 0 0 C D /C W C S Æ S H

flash 64m

Contextual Info: MEMORIES Mask ROMs C a p a c ity Access time C o nfig u ra tio n 120ns 100ns 80ns 150ns 256kj I 32k x 8 ] LH53259 12k I 64k x 8 LH53517 128k x 8 LH530800A LH531V00 1M LH531024 64k x 16 i LH532100B-1 256k x 8 ! LH532100B 2M JEDEC standard EPROM pinout 128k x 161

MB834000

Abstract: M5M23160 MB834100 MB838000 MB832000 SGS M27C256 I27C256 KM23C1010 M27C256 M27C256 intel
Contextual Info: CROSS-REFERENCE GUIDE 1. EPROM CAPACITY CONFIGRUATION MACRONIX INTEL AMD N.S. S.G.S. 256K 32K x 8 MX27C256 i27C256 Am27C256 NM27C256 M27C256 512K 64K x 8 MX27C512 i27C512 Am27C512 NM27C512 M27C512 32K x 16 MX27C516 128K x 8 MX27C1000 i27C010 Am27C010 NM27C010

Contextual Info: MEMORIES ★ Capacity Configuration * 1 C om patible with 4 M -bit flash m em ories from A d vanced M icro D evices, Inc. * 2 C om patible with 4 M -bit flash m em ories from Intel Corp. A c c e s s tim e Under development MEMORIES ★ Under development Access time

Contextual Info: C M O S 3 2 M 4 M x 8 /2 M x 1 6 M R O M FEATURES PIN CONNECTIONS • 4,194,304 words (Byte mode) x 2,097,152 words (Word mode) x 8 bit organization TOP VIEW 44-PIN SOP S A-I8 C 43 —I a 19 CM O 1• 2 < NCC E L 16 bit organization "N 44 A17IZ 3 42 Zl Ag

IR2E27A

Abstract: IR2C53 IR2E02 IR2E27 IR2E10 IR3N34 IR2E31A IR2E01 IR2C07 ir2e31
Contextual Info: lndeX Model No. ARM7D CPU Core28,32,33 ARM7DM 28,33 CMOS CMOS CMOS CMOS 76 5A A F G 44 44 44 44 ID1 series ID2 series ID3 seríes ID21K064 ID21K128 ID21K256 ID21K512 ID21M010 ID21M015 ID21M020 ID21M040 ID22K256 ID22K512 ID22M010 ID22M020 ID22M040 ID22M080

Contextual Info: CMOS 3 2 M 4 M x 8/2 M x 16 MROM FEATURES • 4,194,304 words x 8 bit organization (Byte mode) 2,097,152 words x 16 bit organization (Word mode) • Access time: 150 ns (MAX.) • Power consumption: Operating: 357.5 mW (MAX.) Standby: 550 \i\N (MAX.) • Static operation

LHMN5

Abstract: sharp mask rom 44-pin LH5332600N 2MX16 LH5332600 LH5332600T LH5332C00D LH535
Contextual Info: LH5332600 • Description High-speed 32M-bit Mask-Programmable ROM Pin Connections . The LH5332600N/T User’s No. : LHMN56XX/LHMN5FXX is a CMOS 32M-bit mask-programmable ROM organized as 4 194 3 0 4 X 8 bits (Byte mode) or 2 097 152 X 16 bits (Word mode) that can be selected by BYTE input pin.

IR2E01

Abstract: LR4087 LZ8420M LZ9GG13 LI3160 IR2C36 LZ2423A SM8205 LZ9GG13M LR39901
Contextual Info: Index Model No. A R M 7 D C PU C o re B i-C M O S 1 28 4 0 ,4 2 C 62 IR 3 Y 1 2 A 50 LH1532 49 LH 531V 00 2.4 IR 2 E 2 8 62 IR 3 Y 1 4 50 LH1536 49 LH 532000B 3,4 IR 2 E 2 9 62 IR 3 Y 1 5 50 LH 1540A 49 L H 5 3 2 00 0 B -1 3,4 IR 2 E 3 0 62 IR 3 Y 1 6 50