LH538P00B Search Results

L D O Device Name 23 330 A1 6C

Abstract: sharp 8mbit rom
Contextual Info: LH538P00B FEATURES • 1,048,576 words x 8 bit organization Byte mode 524,288 words x 16 bit organization (Word mode) • Access time: 120 ns (MAX.) • Power consumption: Operating: 330 mW (MAX.) Standby: 550 (iW (MAX.) • Static operation • TTL compatible I/O

Contextual Info: LH538P00B FEATURES • 1,048,576 words x 8 bit organization Byte mode 524,288 words x 16 bit organization (Word mode) • Access time: 120 ns (MAX.) • Power consumption: Operating: 330 mW (MAX.) Standby: 550 (iW (MAX.) • Static operation • TTL compatible I/O

42-PIN

Abstract: 44-PIN 48-PIN LH538
Contextual Info: CMOS 8M 1M x 8/512K × 16 Mask-Programmable ROM LH538P00B FEATURES • 1,048,576 words × 8 bit organization (Byte mode) 524,288 words × 16 bit organization (Word mode) • Access time: 120 ns (MAX.) • Power consumption: Operating: 330 mW (MAX.) Standby: 550 µW (MAX.)

MB8316200

Abstract: uPD23C4000S TC533200 23C4000C UPD23C4000 23C32000a 624116 HN62318/338B
Contextual Info: MEMORY ICS FUNCTION GUIDE 3. CROSS REFERENCE GUIDE Density 4M bit 8M bit Samsung NEC Hitachi Sharp Toshiba Fujitsu K M 23C4000C UPD23C4001EB HN62344B LH534700 TC534000C M B834000A K M 23C4100C UPD23C4000S HN62444 LH534600B TC534200C M B834200A K M 23C 4; OOCET UPD23C4000S

536G

Abstract: LH534600
Contextual Info: MEMORIES • Mask ROMs Process Capacity * Configuration words X bits Pinout Access time Model No. (ns) MIN. Supply current (mA) MAX. Supply voltage (V) (ns) MAX. User's No. Cycle tima Package 256k 32k X 8 J LH53259D/N/T L H 5359X X 150 25 5 ± 10% 28DIP/28SOP/28TSOP(I)

lh57257

Abstract: IR2E31 IR2E01 IR2C07 IR2E27 IR2E24 IR2E19 IR2E31A IR3n06 IR2E02
Contextual Info: Index Model No. ARM7D CPU Core Bi-CMOS 1 27 40,42 _ _ CMOS CMOS CMOS CMOS CMOS 4A 5A 8 A AH D ID1 Series ID2 Series 40,42 40.42 40,42 40,42 40 B ü.’1*"! 14,15 14 m IR2339 IR2403 IR2406 IR2406G IR2410 IR2411 IR2415 IR2419 IR2420 IR2422 IR2425 IR2429

flash 64m

Contextual Info: MEMORIES Mask ROMs C a p a c ity Access time C o nfig u ra tio n 120ns 100ns 80ns 150ns 256kj I 32k x 8 ] LH53259 12k I 64k x 8 LH53517 128k x 8 LH530800A LH531V00 1M LH531024 64k x 16 i LH532100B-1 256k x 8 ! LH532100B 2M JEDEC standard EPROM pinout 128k x 161

Contextual Info: MEMORIES ★ Capacity Configuration * 1 C om patible with 4 M -bit flash m em ories from A d vanced M icro D evices, Inc. * 2 C om patible with 4 M -bit flash m em ories from Intel Corp. A c c e s s tim e Under development MEMORIES ★ Under development Access time

IR2E27A

Abstract: IR2C53 IR2E02 IR2E27 IR2E10 IR3N34 IR2E31A IR2E01 IR2C07 ir2e31
Contextual Info: lndeX Model No. ARM7D CPU Core28,32,33 ARM7DM 28,33 CMOS CMOS CMOS CMOS 76 5A A F G 44 44 44 44 ID1 series ID2 series ID3 seríes ID21K064 ID21K128 ID21K256 ID21K512 ID21M010 ID21M015 ID21M020 ID21M040 ID22K256 ID22K512 ID22M010 ID22M020 ID22M040 ID22M080

Contextual Info: CMOS 8M 1 M x 8/512K x 16 Mask-Program m able ROM LH 538P00B FEATURES • 1,048,576 words x 8 bit organization (Byte mode) 524,288 words x 16 bit organization (Word mode) • Access time: 120 ns (MAX.) PIN CONNECTIONS 42-PIN DIP TOP VIEW / ^18 □ 1• 42 □ NC