LH53V32500 Search Results

Contextual Info: LH53V32500 FEATURES • 4,194,304 words x 8 bit organization Byte mode TOP VIEW 44-PIN SOP S Standby: 108 |iW (MAX.) A-I8 C 43 —I a A 1 7 IZ 3 42 ^ 7 C 4 41 Zl Ag 5 40 Zl A10 6 39 ZI A-, -, 7 38 Zl a 12 8 37 Z IA , 3 9 36 ZI a a • Three-state outputs

D1133

Contextual Info: CMOS 32M 4M x 8/2M × 16 3 V-Drive MROM LH53V32500 FEATURES • 4,194,304 words × 8 bit organization (Byte mode) 2,097,152 words × 16 bit organization (Word mode) • Access time: 150 ns (MAX.) • Power consumption: Operating: 126 mW (MAX.) Standby: 108 µW (MAX.)

Contextual Info: LH53V32500 FEATURES • 4,194,304 words x 8 bit organization Byte mode 2,097,152 words x 16 bit organization (Word mode) CMOS 32M (4M x 8/2M x 16) 3 V-Drive MROM PIN CONNECTIONS 4 4 -P IN S O P • Static operation • Three-state outputs - 4 4 □ a C 4 3

44-PIN

Abstract: 48-PIN
Contextual Info: LH53V32500 FEATURES • 4,194,304 words x 8 bit organization Byte mode 2,097,152 words × 16 bit organization (Word mode) • Access time: 150 ns (MAX.) • Power consumption: Operating: 126 mW (MAX.) Standby: 108 µW (MAX.) • Static operation • Three-state outputs

LHMN5

Abstract: 48TSOP LH5332600 LH5332600N LH5332600T LH5332C00D TSOP048-P-1218 LH5332500 2sj au LHMV
Contextual Info: NBA/ INFORMATION LH5332600 • High-speed 32M-bit Mask-Programmable ROM Pin Connections Description The LH5332600N/T User's No. : LHMN56XX/LHMN5FXX is a CM OS 32M-bit mask-programmable ROM organized as 4 194 304X8 bits (Byte mode) or 2 097 152X 16 bits (Word

536G

Abstract: LH534600
Contextual Info: MEMORIES • Mask ROMs Process Capacity * Configuration words X bits Pinout Access time Model No. (ns) MIN. Supply current (mA) MAX. Supply voltage (V) (ns) MAX. User's No. Cycle tima Package 256k 32k X 8 J LH53259D/N/T L H 5359X X 150 25 5 ± 10% 28DIP/28SOP/28TSOP(I)

lh57257

Abstract: IR2E31 IR2E01 IR2C07 IR2E27 IR2E24 IR2E19 IR2E31A IR3n06 IR2E02
Contextual Info: Index Model No. ARM7D CPU Core Bi-CMOS 1 27 40,42 _ _ CMOS CMOS CMOS CMOS CMOS 4A 5A 8 A AH D ID1 Series ID2 Series 40,42 40.42 40,42 40,42 40 B ü.’1*"! 14,15 14 m IR2339 IR2403 IR2406 IR2406G IR2410 IR2411 IR2415 IR2419 IR2420 IR2422 IR2425 IR2429

LH231G

Abstract: lh5348 LH538b LH2326 lh5s4 LHMN5 lh5359 lh5348xx lh537 LH235
Contextual Info: MEMORIES ★Under development • M ask ROMs SlpÉHRfi Bonflgmllan jvorai x d m i NMOS <"^g|g|ï|ïi£- User1* No. sssysr Sllpjiijp 1 currant mA MAX. ■ Paefcagfe ft- • 64k 8k x 8 LH2389D LH2369XX 200 60 5 ± 10% 28DIP 128k 16k x 8 LH23128D LH2326XX 200

lh5s4

Abstract: lh537 48-TSOP LH5s 42-DIP 48TSOP1 LH5364P00D LH538 LH5S46
Contextual Info: MEMORIES • Mask ROM Specific Pinout ★ U n d e rd e v e lo p m e n t • 3 V 3 .3 V operation Access time B it C a p a c ity configuration 1M x8 2M x 8/x 16 4M x 8/x 16 8M x 8/x 16 16M x 8/x 16 32 M x 8/x 16 64M 128M * x 8/x 16 x 16 Readable at 2.7 V.

A-1435

Contextual Info: • 4,194,304 words x 8 bit organization Byte mode 2,097,152 words x 16 bit organization (Word mode) • Access time: 150 ns (MAX.) • Power consumption: Operating: 126 mW (MAX.) Standby: 108 (iW (MAX.) • Static operation • Three-state outputs • Low power supply: 2.7 V to 3.6 V

flash 64m

Contextual Info: MEMORIES Mask ROMs C a p a c ity Access time C o nfig u ra tio n 120ns 100ns 80ns 150ns 256kj I 32k x 8 ] LH53259 12k I 64k x 8 LH53517 128k x 8 LH530800A LH531V00 1M LH531024 64k x 16 i LH532100B-1 256k x 8 ! LH532100B 2M JEDEC standard EPROM pinout 128k x 161

MB834000

Abstract: M5M23160 MB834100 MB838000 MB832000 SGS M27C256 I27C256 KM23C1010 M27C256 M27C256 intel
Contextual Info: CROSS-REFERENCE GUIDE 1. EPROM CAPACITY CONFIGRUATION MACRONIX INTEL AMD N.S. S.G.S. 256K 32K x 8 MX27C256 i27C256 Am27C256 NM27C256 M27C256 512K 64K x 8 MX27C512 i27C512 Am27C512 NM27C512 M27C512 32K x 16 MX27C516 128K x 8 MX27C1000 i27C010 Am27C010 NM27C010

LQ070T5BG01

Abstract: LM24P20 LM162KS1 BSCR86L00 IR2C07 LM5Q31 IR3Y29B BSCU86L60 lq6bw lq6bw506
Contextual Info: INDEX 1 0 4 - 1 0 9 _ DC_ GL1PR112.69 GL3KG63. 66 GL5EG41.66 1 0 4 - n 0 5 O o c .113 DC1B1CP. 100 GL1PR135.69 GL3KG8. 66

Contextual Info: MEMORIES ★ Capacity Configuration * 1 C om patible with 4 M -bit flash m em ories from A d vanced M icro D evices, Inc. * 2 C om patible with 4 M -bit flash m em ories from Intel Corp. A c c e s s tim e Under development MEMORIES ★ Under development Access time

48 tsop flash pinout

Abstract: LH23512
Contextual Info: MEMORIES Mask ROMs ^Under development Capacity Pinout Model No. Configuration Access time ns 55 1 64k !- 1 8k x 8 128k 16k x ! 256k 32k x 8 |- -) [ 512k 64k x 8 b — I 80 100 120 150 200 Package 250 500 □ LH2369 28 LH23255 28 □ LH53259 28 28 38(1)

lh5s4

Abstract: LH537 lh5s4p lh5s4R lh5s46 LH538 44SOP lh533200 LH5s 5g85
Contextual Info: MASK ROM ☆ New product ★ • M Capacity ASK F O M S Bit Pinout* configuration Model No. LH53V4T00E J J x8 4M x 16 x 8/ x 16 x8 8M x 8/ x 16 LH53V4ROOAN/AT LH53V4R00N/T J J J LH53V4YG0N/E LH53H4100D/N LH534700D/N LH534R00BD/BN LH53V4B00T J J F F LH534A00T

IR2E27A

Abstract: IR2C53 IR2E02 IR2E27 IR2E10 IR3N34 IR2E31A IR2E01 IR2C07 ir2e31
Contextual Info: lndeX Model No. ARM7D CPU Core28,32,33 ARM7DM 28,33 CMOS CMOS CMOS CMOS 76 5A A F G 44 44 44 44 ID1 series ID2 series ID3 seríes ID21K064 ID21K128 ID21K256 ID21K512 ID21M010 ID21M015 ID21M020 ID21M040 ID22K256 ID22K512 ID22M010 ID22M020 ID22M040 ID22M080

LHMN5

Abstract: sharp mask rom 44-pin LH5332600N 2MX16 LH5332600 LH5332600T LH5332C00D LH535
Contextual Info: LH5332600 • Description High-speed 32M-bit Mask-Programmable ROM Pin Connections . The LH5332600N/T User’s No. : LHMN56XX/LHMN5FXX is a CMOS 32M-bit mask-programmable ROM organized as 4 194 3 0 4 X 8 bits (Byte mode) or 2 097 152 X 16 bits (Word mode) that can be selected by BYTE input pin.

IR2E01

Abstract: LR4087 LZ8420M LZ9GG13 LI3160 IR2C36 LZ2423A SM8205 LZ9GG13M LR39901
Contextual Info: Index Model No. A R M 7 D C PU C o re B i-C M O S 1 28 4 0 ,4 2 C 62 IR 3 Y 1 2 A 50 LH1532 49 LH 531V 00 2.4 IR 2 E 2 8 62 IR 3 Y 1 4 50 LH1536 49 LH 532000B 3,4 IR 2 E 2 9 62 IR 3 Y 1 5 50 LH 1540A 49 L H 5 3 2 00 0 B -1 3,4 IR 2 E 3 0 62 IR 3 Y 1 6 50