MARKING T4C Search Results

Contextual Info: PRELIMINARY |W|IC=RC3N 512K M T4C 8 512/3 L WIDE DRAM X 8 512K x 8 DRAM WIDE DRAM LOW POWER, EXTENDED REFRESH FEATURES PIN ASSIGNMENT Top View OPTIONS 28-Pin ZIP (DB-3) 28-Pin SOJ (DC-4) MARKING • Timing 60ns access 70ns access 80ns access • MASKED WRITE

Contextual Info: M T4C4003J lEG X 4 DRAM M IC R O N 1 MEG DRAM X 4 DRAM DRAM STATIC COLUMN FEATURES PIN ASSIGNMENT (Top View OPTIONS 20-Pin ZIP (DC-1) (DB-2) DQ1 DQ2 WE RAS A9 MARKING • Timing 70ns access 80ns access • Packages Plastic SOJ (300 mil) Plastic ZIP (350 mil)

Contextual Info: • h ÉidMiuiilBHááttaSflÉ BflE D MICRON TECHNOLOGY INC b llIS H T G G O E Tll =i ■ MRN ADVANCE ÉtaB*6â*ù^ÂeeÂfcâi - uMMüff T4C-2Z-/< 16K X 16 SRAM SYNCHRONOUS SRAM W ITH CLOCKED, REGISTERED INPUTS FEATURES • • • • OPTIONS MARKING « Timing

Contextual Info: MICRON B M T4C16256/7/8/9 L 256K X 16 WIDE DRAM BCMICDNDUCTaH. WC WIDE DRAM 256K x 16 DRAM LOW POWÉR, EXTENDED REFRESH FEATURES MARKING • T im ing 60ns access 70ns access 80ns access • W rite Cycle Access BYTE o r W ORD via WE nonm askable BYTE or W ORD via CAS

Contextual Info: ADVANCE MT4 L C2M8A1/2 2 MEG X 8 WIDE DRAM MICRON WIDE DRAM 2 MEG x 8 DRAM 5.0V, FAST-PAGE-MODE (MT4C2M8A1/2) 3.0/3.3V, FAST-PAGE-MODE (MT4LC2M8A1/2) FEATURES PIN ASSIGNMENT (Top View) OPTIONS MARKING • Timing 60ns access 70ns access 80ns access -6 -7 -8

MT8C

Contextual Info: M IC R O N MT8C9026 1MEG x 9 DRAM DRAM MODULE STATIC COLUMN PIN ASSIGNMENT (Top View OPTIONS MARKING • Timing 80ns access 100ns access 120ns access • Packages: Leaded 30 -pin SIP Leadless 30-pin SIMM -10 -12 MN M GENERAL DESCRIPTION The MT8C9026 is a randomly accessed solid-state

Contextual Info: ADVANCE MT4 L C2M8A1/2 2 MEG X 8 WIDE DRAM M IC R O N WIDE DRAM 2 MEG X 8 DRAM 5.0V, FAST-PAGE-MODE (MT4C2M8A1/2) 3.0/3.3V, FAST-PAGE-MODE (MT4LC2M8A1/2) FEATURES PIN ASSIGNMENT (Top View) OPTIONS MARKING • Timing 60ns access 70ns access 80ns access -6 -7

Contextual Info: ADVANCE MT4 L C2M8B1/2 S 2 MEG X 8 WIDE DRAM M ICRO N WIDE DRAM 2 MEG X 8 DRAM 5.0V SELF REFRESH ÍMT4C2M8B1/2 S) 3.0/3.3V, SELF REFRESH (MT4LC2M8B1/2 S) FEATURES PIN A SSIG N M EN T (Top View) OPTIONS MARKING • Timing 60ns access 70ns access 80ns access

Contextual Info: ADVANCE M T4 L C 2M 8B 1/2 2 MEG X 8 W ID E DRAM I^ IIC R D N WIDE DRAM 2 MEG x 8 DRAM 5.0V FAST-PAGE-MODE (MT4C2M8B1/2) 3.0/3.3V, FAST-PAGE-MODE (MT4LC2M8B1/2) FEATURES PIN ASSIGNMENT (Top View) OPTIONS MARKING • Timing 60ns access 70ns access 80ns access

t3d01

Abstract: pin configuration of IC 1619 cp LM 3177 C16-256 MT4C16257
Contextual Info: PRELIMINARY M T 4C 16256/7/8/9 S 256K X 16 WIDE DRAM |U |I C R O N WIDE DRAM 2 5 6 K X 16 DRAM FAST-PAGE-MODE SELF REFRESH FEATURES OPTIONS P IN A S S IG N M E N T 4 0 -P in S O J T o p 4 0 -P in MARKING • Timing 70ns access -7 80ns access -8 • Write Cycle Access

Contextual Info: ADVANCE M T4C 1672 64K x 16 DRAM DRAM FAST PAGE MODE, DUAL CAS FEATURES • Industry standard xl6 pinouts, timing, functions and packages • High performance, CMOS silicon gate process • Single +5V±10% power supply • Low power, 3mW standby; 350mW active, typical

Contextual Info: ADVANCE M T4C 10016/7 16 MEG x1 DRAM FAST PAGE MODE: MT4C10016 STATIC COLUMN: MT4C10017 FEATURES • Industry standard xl pinout, timing, functions and packages • High performance, CMOS silicon gate process • Single power supply: +5V±10% or +3.3V±10%

Contextual Info: ADVANCE CZR M T4C 10016/7 16 MEG X 1 DRAM FAST PAGE MODE: MT4C10016 STATIC COLUMN: MT4C10017 FEATURES • Industry standard xl pinout, timing, functions and packages • High performance, CMOS silicon gate process • Single power supply: +5V±10% or +3.3V±10%

Contextual Info: ADVANCE M IC R O N M T4C40004/5 4 MEG x 4 DRAM FAST PAGE MODE: MT4C40004 STATIC COLUMN: MT4C40005 FEATURES • Industry standard x4 pinout, timing, functions and packages • High performance, CMOS silicon gate process • Single power supply : +5V±10% or +3.3V±10%

4C4256

Contextual Info: M T4C4256 L 256K X 4 DRAM |V |IC Z R O N DRAM 256K x 4 DRAM FEATURES • 512-cycle refresh in 8ms (MT4C4256) or 64ms (MT4C4256 L) • Industry-standard x4 pinout, tim ing, functions and packages • High-perform ance CM OS silicon-gate process • Single +5V +10% power supply

Contextual Info: M T4C1006J MICRON I 4M E GX1 D R A M DRAM 4 MEG x 1 DRAM • FEATURES • Industry-standard x l pinout, timing, functions and packages • High-performance CMOS silicon-gate process • Single +5V ±10% power supply • Low power, 3mW standby; 225mW active, typical

Contextual Info: PRELIMINARY M T4C4M 4A1/B1 4 M EG X 4 DRAM v iic n o N DRAM 4 MEG X 4 DRAM FEATURES • Industry-standard x4 pinout, timing, functions and packages • High-performance CMOS silicon-gate process • Single power supply : +5V ±10% • Low pow'er, 3mW standby; 325mW active, typical (A l

1004J

Contextual Info: M T4C1004J L 4 MEG X 1 DRAM DRAM 4 MEG X 1 DRAM LOW POWER, EXTENDED REFRESH FEATURES • Industry standard x l pinout, timing, functions and packages • High-performance, CM OS silicon-gate process • Single +5V ±10% power supply • All inputs, outputs and clocks are fully TTL

EDO DRAM

Abstract: MT4C4007JDJ-6L MT4C4007JDJ-6
Contextual Info: 1 MEG x 4 EDO DRAM V IIC Z R C H V S DRAM M T4C 4007J FEATURES PIN ASSIGNMENT (Top View Single+5V ±10% power supply JEDEC-standard pinout and packages High-performance CMOS silicon-gate process All inputs, outputs and clocks are TTL-compatible Refresh modes: RAS#-ONLY, CAS#-BEFORE- RAS#

MT4C1004

Contextual Info: M T4C1004J S 4 MEG X 1 DRAM (M IC R O N DRAM 4 MEG x 1 DRAM 5V, STANDARD OR SELF REFRESH • 1,024-cycle refresh distributed across 16ms (MT4C1004J) or 128ms (M T4C1004J S only) • Industry-standard pinout, tim ing, functions and packages • High-perform ance CM OS silicon-gate process

Contextual Info: M T 4 C 4 0 0 1 J S 1 MEG x 4 DRAM |U|(=RON DRAM 1 MEG x 4 DRAM 5V, STANDARD OR SELF REFRESH FEATURES • 1,024-cycle refresh distributed across 16ms (M T4C4001J) or 128ms (M T4C4001J S) • Industry-standard pinout, timing, functions and packages • High-perform ance CM OS silicon-gate process

MT4C1004

Contextual Info: MT4C1004J S 4 MEG X 1 DRAM |U|K=RON DRAM 4 MEG X 1 DRAM FEATURES • 1,024-cycle refresh distributed across 16ms (M T4C1004J) or 128ms (MT4C1004J S only) • Industry-standard pinout, tim ing, functions and packages • High-perform ance CM OS silicon-gate process

T4C16257DJ

Abstract: t4c16257 T4C16257DJ-7
Contextual Info: l^ lld R O N 256K DRAM M T4C 16257 X 16 DRAM 256K x 16 DRAM 5V, FAST PAGE MODE • Industry-standard x l6 pinouts, timing, functions and packages • High-perform ance CM OS silicon-gate process • Single +5V ±10% power supply* • Low power, 3m W standby; 375m W active, typical

Contextual Info: M ’ I C R O N 1 MEG X 1 FPM D R A M DRAM M T4C 1004J FEATURES • 1,024-cycle refresh distributed across 16ms M T4C1004J or 128ms (M T4C1004J L only) • Industry-standard pinout, tim ing, functions and packages • High-perform ance CM OS silicon-gate process